The present invention relates generally to memory devices and in particular the present invention relates to read only memory (ROM) embedded in a dynamic random access memory (DRAM).
Semiconductor memory systems are comprised of two basic elements: memory storage areas and memory control areas. DRAM, for example, includes a memory cell array, which stores information, and peripheral circuitry, which controls the operation of the memory cell array.
DRAM arrays are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor. The capacitor holds the value of each cell, namely a xe2x80x9c1xe2x80x9d or a xe2x80x9c0,xe2x80x9d as a charge on the capacitor. Because the charge on a capacitor gradually leaks away, DRAM capacitors must be refreshed on a regular basis. A memory device incorporating a DRAM memory includes logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static.
The transistor of a DRAM cell is a switch to let control circuitry for the RAM either read the capacitor value or to change its state. The transistor is controlled by a row line coupled to its gate connection. In a read operation, the transistor is activated and sense amplifiers coupled to bit lines (column) determine the level of charge stored in the memory cell capacitor, and reads the charge out as either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d depending upon the level of charge in the capacitor. In a write operation, the sense amplifier is over-powered and the memory cell capacitor is charged to an appropriate level.
Frequently, as in the case of microprocessors, microcontrollers, and other application specific integrated circuitry (ASICs), it is desired to incorporate read only memory (ROM) together with or in addition to RAM on a single semiconductor wafer. This typically requires the formation of separate additional peripheral circuitry and interconnects for the ROM. The ROM cells and additional circuitry require additional semiconductor wafer space and fabrication process steps that increase the overall costs of device fabrication.
A read only memory (ROM) consists of an array of semiconductor devices (diodes, bipolar or field-effect transistors), which interconnect to store an array of binary data (ones or zeros). A ROM basically consists of a memory array of programmed data and a decoder to select the data located at a desired address in the memory array.
Three basic types of ROMs are mask-programmable ROMs, erasable programmable ROMs (EPROMs) and field-programmable ROMs (PROMs). The data array is permanently stored in a mask-programmable ROM, at the time of manufacture, by selectively including or omitting the switching elements at the row-column intersections in the memory array. This requires a special mask used during fabrication of the integrated circuit, which is expensive and feasible only when a large quantity of the same data array is required. EPROMs use a special charge-storage mechanism to enable or disable the switching elements in the memory array. In this case, appropriate voltage pulses to store electrical charges at the memory array locations are provided. The data stored in this manner is generally permanent until it is erased using ultraviolet light allowing it to once again be programmed. PROMs are typically manufactured with all switching elements present in the array, with the connection at each row-column intersection being made by means of either a fuse element or an anti-fuse element. In order to store data in the PROM, these elements (either the fuse or the anti-fuse, whichever are used in the design) are selectively programmed using appropriate voltage pulses supplied by a PROM programmer. Once the elements are programmed, the data is permanently stored in the memory array.
Programmable links have been used extensively in programmable read only memory (PROM) devices. Probably the most common form of programmable link is a fusible link. When a user receives a PROM device from a manufacturer, it usually consists of an X-Y matrix or lattice of conductors or semiconductors. At each crossover point of the lattice a conducting link, call a fusible link, connects a transistor or other electronic node to this lattice network. The PROM is programmed by blowing the fusible links to selected nodes and creating an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data that the user wishes to store in the PROM. By providing an address the data stored on a node may be retrieved during a read operation.
In recent years, a second type of programmable link, call an anti-fuse link, has been developed for use in integrated circuit applications. Instead of the programming mechanism causing an open circuit as in the case with fusible links, the programming mechanism in an anti-fuse circuit creates a short circuit or relatively low resistance link. Thus the anti-fuse link presents an open circuit prior to programming and a low resistance connection after programming. Anti-fuse links consist of two electrodes comprised of conductive and/or semiconductive materials and having some kind of a dielectric or insulating material between them. During programming, the dielectric in between the conductive materials is broken down by predetermined applied voltages, thereby electrically connecting the conducting and/or semiconducting materials together.
Like RAM cells, ROM cells need to store either a data 1 or a data 0. Processing factors, however, may limit the ROM cell to only one program state. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a ROM-embedded-DRAM which can be fabricated with single state ROM cells.
The above-mentioned problems with ROM embedded DRAM""s and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises a plurality of memory cell capacitors. A portion of the plurality of memory cell capacitors is programmed in a non-volatile manner to a first data state. Digit lines are selectively couplable to the plurality of memory cell capacitors, and sense circuitry is coupled to the digit lines. The sense circuitry is biased to detect a second data state in an absence of a programmed memory cell capacitor coupled to the digit lines.
A read only memory (ROM) embedded dynamic random access memory (DRAM) device comprises a plurality of DRAM cell capacitors programmed as ROM cells in a non-volatile manner to a first data state. Sense circuitry is coupled to first and second digit lines. The sense circuitry is biased to detect a second data state on the first digit line in an absence of a programmed memory cell capacitor coupled to the first digit line.
In another embodiment, a memory device comprises a plurality of memory cell capacitors, wherein a portion of the plurality of memory cell capacitors is programmed in a non-volatile manner to a first data state. Digit lines are selectively couplable to the plurality of memory cell capacitors, and sense circuitry is coupled to the digit lines. A reference cell is coupled to the sense circuitry to force a detection of a second data state in an absence of a programmed memory cell capacitor coupled to the digit lines.
A read only memory (ROM) embedded dynamic random access memory (DRAM) device comprises a plurality of DRAM cell capacitors programmed as ROM cells in a non-volatile manner to a first data state. Sense circuitry is coupled to first and second digit lines, and a reference cell is coupled to the sense circuitry to force a detection of a second data state in an absence of a programmed memory cell capacitor coupled to the digit lines.
In another embodiment, a memory device comprises a plurality of memory cell capacitors programmed in a non-volatile manner to a first data state, and a bias circuit coupled to the sense circuitry to force a detection of a second data state in an absence of a programmed memory cell capacitor coupled to digit lines.
In yet another embodiment, a read only memory (ROM) embedded dynamic random access memory (DRAM) device comprises a plurality of DRAM cell capacitors programmed as ROM cells in a non-volatile manner to a first data state. A bias circuit is coupled to sense circuitry to force a detection of a second data state in an absence of a programmed memory cell capacitor coupled to digit lines.